1. Field of the Invention
The present invention relates to a differential logic family and more particularly to a low voltage, high speed, differential logic family formed from bipolar or field effect transistors, configured for relatively low voltage operation which provides relatively reduced power consumption and part count relative to known differential logic families.
2. Description of the Prior Art
Various logic families are known for performing standard Boolean logic functions, such as AND, OR, NOT, exclusive OR functions, as well as non-Boolean functions, such as storage and buffering. Both bipolar and metal oxide semiconductor (MOS) logic families are known. An example of a bipolar logic family is transistor - transistor - logic (TTL). An example of MOS logic family is complementary metal oxide semiconductor (CMOS) logic. Bipolar logic circuits are known to have relatively high speed but suffer from relatively high power consumption. CMOS logic circuits are known to have relatively low power consumption but are relatively slower than bipolar logic families.
In order to further increase the switching speeds of bipolar logic devices, emitter coupled logic (ECL) circuits have been developed. Examples of ECL logic circuits are disclosed in U.S. Pat. Nos. 4,737,664; 4,760,289; 4,714,841; 4,751,404; 5,065,050; 5,250,860; 5,610,539 and 5,684,416. Such ECL circuits, also known as current mode logic (CML) circuits, normally include one or more pairs of differentially connected transistors with the emitters tied together forming differential pairs. Inputs are applied to the base terminals of the differential pair. The collectors of the bipolar transistors forming the differential pair are known to be connected to load resistors while the emitters are connected to a constant current source. In order to maintain a relatively fast switching speed, the collectors of the differential pair are generally buffered from the load and used to drive interstage buffers, configured as static emitter followers, which, in turn, are known to each be connected to a constant current source. Even though such ECL logic circuits are known to provide relatively high speed operation since the bipolar transistors used in these logic families are not saturated, the constant current sources in the output stage result in relatively high power consumption.
Another consideration of CML logic families is the operating voltage level of the device. In order to accommodate multiple inputs, multiple levels of differential pairs are known to be connected in a cascode or "stacked" configuration, for example, as disclosed in U.S. Pat. No. 5,075,574. Unfortunately, the operating voltage puts constraints on the number of levels in the circuit. The minimum supply voltage is the sum of all stacked base-mitter voltages (VBE, with VBE=VCE) and the voltage across the current source element (VCS), which can be an active current source in the form of a BJT with emitter degeneration resistor, or a passive device in the form of a resistor. For example, FIG. 1 of the '574 patent illustrates a three level circuit in a cascode configuration which requires a 5.0 supply voltage. In order to reduce the supply voltage requirement, the number of levels or stacked VBE's of the circuit need to be reduced. In order to maintain the same number of inputs with fewer levels, multiple inputs are connected to the differential pair by way of input diodes, such as Schottky barrier diodes, for example, as illustrated in FIG. 2 of the '574 patent.
FIGS. 3 and 4 of the '574 patent illustrate multiple level differential logic circuits. In particular, FIG. 3 illustrates a silicon three level differential logic circuit for use with a 3.4 volt supply voltage. FIG. 4 of the '574 patent illustrates the use of Schottky barrier diodes at the bases of the differential pair to further reduce the power supply voltage requirement to 3.0 volts. Since the input diodes introduce a voltage drop, input diodes are connected to both bipolar transistors forming the differential pair to balance the DC operating point of the differential pair. Such a configuration increases the part count and thus the complexity of the device.
As mentioned above, known ECL logic circuits offer the highest switching speed but unfortunately require interstage buffers with constant current sources. These constant current sources result in relatively high power consumption of the device. In addition, known ECL gate circuits, configured for lower voltage and multiple input operation, require input diodes connected to both bipolar transistors forming the transistor pair, thus increasing the part count and power consumption of such circuits. Thus, prior art is improved by reducing power consumption and complexity in which the gate circuits utilize fewer input diodes and biasing resistors relative to other logic families.